[{"content":"AI hardware scaling now forces tighter integration between memory expansion, clock distribution, advanced packaging, and grid power stability\nEngineers who have tried to add capacity to a server memory subsystem without breaking latency or bandwidth budgets already understand the pressure. Generative AI workloads store trillions of parameters that must be accessed at low latency, and conventional DDR channels cannot keep up. This week several publications quantify what changes when memory, timing, and power delivery are treated as a single system-level problem rather than separate board-level tasks.\nThe common thread is that AI platforms exceed the physical and electrical assumptions built into earlier server designs. Platform requirements now include new interconnect protocols, tighter clock skew budgets, pitch translation between interposer and PCB, and acceptance that instantaneous power draw can swing faster than grid operators have planned for. These constraints appear together in the same designs rather than in isolation.\nThe result is that layout, signal integrity, and thermal decisions made early in the floor-planning stage now determine whether the final system meets its performance targets. Component selections that ignore these interactions produce boards that pass functional test yet fail in the target workload.\nThe essentials CXL Type 3 memory changes platform requirements Applications that train or serve large language models need both higher capacity and effective bandwidth than traditional server channels provide. CXL Type 3 devices attach as memory expanders rather than as accelerators, so the host platform must supply coherent memory semantics, appropriate power delivery, and PCB routing that preserves signal integrity over the added distance.\nChorus 2 clock generators tighten timing margins for AI fabrics The second-generation device claims 2× lower jitter and up to 2.5× lower output skew compared with the prior Chorus family while adding wider spread-spectrum support. These parameters matter when multiple high-speed interfaces must remain phase-aligned across large AI accelerator arrays; the improvement directly reduces the guard-band engineers must allocate for clock uncertainty.\nCoWoP packaging shifts the interposer-to-PCB interface problem Part 2 of the CoWoP series examines pitch translation between the fine-pitch interposer and the coarser PCB. The corridor between these two layers now determines both signal integrity and thermal resistance; designers must decide where to place the translation and how many layers are required to maintain return paths without excessive via inductance.\nAI data-center power swings test grid stability Rapid changes in instantaneous load from large GPU clusters create voltage and frequency disturbances that propagate beyond the facility fence. Grid operators and data-center designers must therefore coordinate on ramp-rate limits, on-site storage, and real-time demand response rather than treating compute power as a steady average load.\nSingle Pair Ethernet with power delivery simplifies industrial links The approach combines data and power on one twisted pair, reducing cable count in environments where space and weight matter. The design must still satisfy insertion-loss, return-loss, and power-extraction constraints so that the link remains reliable when motors or solenoids switch nearby.\nDesign debates and tensions One recurring tension is whether memory expansion should occur through CXL-attached devices or through tighter integration inside the package. CXL adds protocol overhead and longer traces, yet it preserves the ability to field-upgrade capacity after the system is deployed. On-package memory removes the trace problem but fixes the capacity at manufacturing time and raises the cost of yield fallout. The data so far favor CXL when the workload batch size varies widely; fixed workloads with known memory footprints lean toward on-package solutions.\nA second tension appears in clock distribution. Lower-jitter MEMS-based generators reduce the number of discrete oscillators, but they still require careful supply decoupling and PCB return paths. The choice between a centralized generator and distributed local oscillators therefore depends on whether board area or power-supply noise is the tighter constraint.\nComponent and industry news Acromag released a Mini PCIe module built around a Zynq UltraScale+ MPSoC for compact FPGA mezzanine use. Melexis introduced the MLX91229 Hall current sensor with second-order sigma-delta output aimed at EV traction inverters where EMI tolerance over longer traces is required. Würth Elektronik added WE-FNCS nanocrystalline sheets for magnetic shielding from 10 Hz to 120 MHz.\nResearch and technical advances No peer-reviewed papers or conference results with quantitative benchmarks appeared in the collected sources this week.\nStandards, compliance, and industry policy No new standards releases or regulatory updates with defined timelines were reported in the collected sources.\nQuick Radar Mini PCIe FPGA module: Acromag’s Zynq UltraScale+ based card targets compact industrial mezzanine applications. Hall sensor with sigma-delta output: Melexis MLX91229 provides digital current sensing tolerant of automotive EMI environments. Nanocrystalline EMI sheets: Würth Elektronik WE-FNCS parts address low-frequency magnetic interference from 10 Hz upward. SPoE reference design guidance: EE Times article outlines practical considerations for combining data and power on a single twisted pair. Atomic-force microscope imaging: Hackaday piece describes surface metrology that does not rely on optical beams. Closing If you have already evaluated CXL Type 3 expanders on a prototype platform, what specific host-controller features turned out to be non-negotiable for stable operation under full AI workload? No traceable practical resource URL was supplied in the collected content, so readers are left to compare their own platform memory maps against the CXL requirements described in the EDN article.\nSources EDN: Why CXL Type 3 memory matters, what your platform must provide - https://www.edn.com/why-cxl-type-3-memory-matters-what-your-platform-must-provide/ Embedded.com: SiTime Upgrades Chorus Clock Generators - https://www.embedded.com/sitime-upgrades-chorus-clock-generators/ EDN: The interposer-to-PCB realization corridor in CoWoP - https://www.edn.com/the-interposer-to-pcb-realization-corridor-in-cowop/ IEEE Spectrum: AI’s Volatile Power Use Quietly Tests Grid Limits - https://spectrum.ieee.org/data-centers-grid-instability EE Times: Design of a Single Pair Ethernet System with Power over Data Lines (SPoE) - https://www.eetimes.com/design-of-a-single-pair-ethernet-system-with-power-over-data-lines-spoe/ Electronics-Lab: Würth Elektronik’s WE-FNCS Targets Low-Frequency EMI Shielding - https://www.electronics-lab.com/wurth-elektroniks-we-fncs-targets-low-frequency-emi-shielding/ Hackaday: Seeing Bacteria, Nanoprisms, and More with an Atomic Force Microscope - https://hackaday.com/2026/07/05/seeing-bacteria-nanoprisms-and-more-with-an-atomic-force-microscope/ EDN: Hall current sensor delivers sigma-delta output - https://www.edn.com/hall-current-sensor-delivers-sigma-delta-output/ Electronic Design: Mini PCIe Module Delivers Compact FPGA Mezzanine Solution - https://www.electronicdesign.com/technologies/industrial/modules/product/55387719/electronic-design-mini-pcie-module-delivers-compact-fpga-mezzanine-solution ","permalink":"https://mixedsignalbrief.com/newsletter/2026-w28/","summary":"\u003cp\u003eAI hardware scaling now forces tighter integration between memory expansion, clock distribution, advanced packaging, and grid power stability\u003c/p\u003e\n\u003cp\u003eEngineers who have tried to add capacity to a server memory subsystem without breaking latency or bandwidth budgets already understand the pressure. Generative AI workloads store trillions of parameters that must be accessed at low latency, and conventional DDR channels cannot keep up. This week several publications quantify what changes when memory, timing, and power delivery are treated as a single system-level problem rather than separate board-level tasks.\u003c/p\u003e","title":"Mixed Signal Brief - Week 28, 2026"},{"content":"AI-driven device complexity is forcing measurable changes in test distribution, system-level validation practices, and process technology roadmaps.\nEngineers who have debugged a marginal power rail only to discover the root cause lay in an unmodeled thermal-RF coupling already understand the problem. When GPU and accelerator die counts rise and heterogeneous integration packs more functions into one package, the old separation between architecture definition and validation collapses. Small shifts in one subsystem now propagate through thermal, power-delivery, and signal-integrity domains before first silicon returns. This week\u0026rsquo;s publications quantify that coupling and show where conventional test flows break first.\nThe practical consequence is that validation effort is migrating earlier in the flow and test content is being redistributed across wafer, package, and system stages. At the same time, process announcements continue to promise density gains that will only increase the validation burden. The engineering question is no longer whether these domains interact, but which assumptions in the current test plan will fail first when they do.\nThe essentials AI workloads increase test content volume. Semiconductor test flows must now accommodate larger volumes of performance, reliability, and quality vectors for GPUs and AI accelerators, shifting test distribution earlier in the manufacturing sequence to keep throughput viable.\nArchitecture and validation are no longer sequential. In tightly integrated consumer and compute systems, thermal, RF, mechanical, and power domains interact so strongly that an architectural change in one area alters failure modes in others, requiring validation models that capture cross-domain coupling from the start.\nEmbedded development processes lag silicon capability. Many teams still rely on fragmented tool chains and late-stage validation even as device complexity rises, creating a gap between what silicon can deliver and what current workflows can reliably verify.\nSub-1 nm process announcements raise validation stakes. IBM\u0026rsquo;s 0.7 nm node demonstration targets partner production within five years, extending the same density trajectory that already strains existing test and validation assumptions.\nProcess integration details matter for yield. Deep ultraviolet lithography steps remain critical enablers inside extreme ultraviolet flows, and any change in their control directly affects defect density at the next node.\nDesign debates and tensions One persistent tension is the allocation of validation effort between pre-silicon modeling and post-silicon measurement. Tighter integration makes late discovery of cross-domain failures more expensive, yet many teams still treat thermal, power, and RF simulations as separate workstreams. Data from recent system-level studies suggest that early co-simulation of these domains reduces the number of respins, but the required tool integration and model fidelity remain project-specific.\nA second debate concerns how much test content can be moved to wafer sort versus package or system test without losing coverage of defects that only appear after assembly. The choice directly affects both capital equipment loading and the risk of shipping marginal parts.\nComponent and industry news Vicfuse released a new UL-class fuse series aimed at AI infrastructure and industrial protection circuits where operating conditions vary across motor drives, transformers, and semiconductor power stages.\nTDK introduced the HAL 13xy family of dual-output 3D Hall-effect switches for automotive motor speed and direction sensing.\nResearch and technical advances Research into paper-based circuit traces demonstrates that conductive patterns can be formed by controlled folding rather than conventional etching. The approach trades conventional PCB tolerances for mechanical flexibility and may suit low-volume sensing or educational hardware where layout iteration cost must stay minimal.\nStandards, compliance, and industry policy No new standards documents with enforceable dates appeared in the collected material this week.\nQuick Radar Iridium 9604 module and kit: Hybrid satellite-cellular-positioning platform released for industrial IoT devices requiring global connectivity without separate radios. Eggtronic-Renesas 500 W microinverter: GaN-based single-stage DC-AC reference platform intended for higher-power photovoltaic modules. PEAK Automotive Ethernet media converter: First device from the brand bridging 100/1000BASE-T1 to standard Ethernet for vehicle test and development. ESP32-P4/C61 AIoT board: Compact module with Wi-Fi 6, Bluetooth 5, MIPI camera and display interfaces plus microSD support. RF ceiling-fan remote hack: Reverse-engineered protocol allows local control that bypasses the original cloud-only interface. Closing When test content volume grows faster than available vector memory on existing ATE, which coverage metrics do you drop first and how do you justify the risk to downstream quality? If you have faced this trade-off on a recent AI accelerator or heterogeneous SoC, compare your approach with the redistribution strategy outlined in the EDN test-distribution article.\nSources EDN: How AI is driving a new paradigm in test distribution - https://www.edn.com/how-ai-is-driving-a-new-paradigm-in-test-distribution/ EDN: Relationship between architecture and validation in system design - https://www.edn.com/relationship-between-architecture-and-validation-in-system-design/ IEEE Spectrum: Make an Origami Circuit Board - https://spectrum.ieee.org/origami-circuit-boards/ EE Times: IBM Shows Sub-1-nm Chips, Targeting Production in 5 Years - https://www.eetimes.com/ibm-shows-sub-1-nm-chips-targeting-production-in-5-years/ EE Times: Deep UV Lithography Processing, the Best Kept Secret of EUV Lithography - https://www.eetimes.com/deep-uv-lithography-processing-the-best-kept-secret-of-euv-lithography/ Embedded.com: From Silicon to Systems: Reimagining the Future of Embedded Engineering - https://www.embedded.com/from-silicon-to-systems-reimagining-the-future-of-embedded-engineering/ ","permalink":"https://mixedsignalbrief.com/newsletter/2026-w27/","summary":"\u003cp\u003eAI-driven device complexity is forcing measurable changes in test distribution, system-level validation practices, and process technology roadmaps.\u003c/p\u003e\n\u003cp\u003eEngineers who have debugged a marginal power rail only to discover the root cause lay in an unmodeled thermal-RF coupling already understand the problem. When GPU and accelerator die counts rise and heterogeneous integration packs more functions into one package, the old separation between architecture definition and validation collapses. Small shifts in one subsystem now propagate through thermal, power-delivery, and signal-integrity domains before first silicon returns. This week\u0026rsquo;s publications quantify that coupling and show where conventional test flows break first.\u003c/p\u003e","title":"Mixed Signal Brief - Week 27, 2026"},{"content":"PCB design tools and power architectures are adapting to tighter integration, faster interfaces, and multiphysics constraints that older flows no longer contain.\nEngineers who have watched a differential pair fail post-layout or a return path collapse under a dense BGA already understand the core issue. Verification now arrives too late when schematic capture, layout, and manufacturing rules remain loosely coupled. Several publications this week quantify how automation layers and integrated analysis change that sequence.\nThe common thread is not new silicon announcements but the practical pressure on layout, thermal paths, and signal integrity when power stages, high-speed serial links, and edge processors share the same substrate. The editions that follow examine where the tooling and component choices actually shift design practice.\nThe essentials Automation layers now catch constraint violations earlier in PCB flows. The described workflow moves rule checking from post-layout verification into schematic capture and iterative layout, reducing the number of respins triggered by differential-pair spacing, return-path discontinuities, or fab limits that were previously discovered only during DFM review.\nGaN three-phase modules shrink inverter footprints for small BLDC drives. The EPC33110 integrates six eGaN FETs, gate drivers, level shifters, and bootstrap circuitry inside a 6 by 6.5 mm QFN, allowing the EPC99132 board to target drone and robotic-wrist applications where board area and switching losses dominate.\nRetimers address reach limits in PCIe 6.0 and CXL 3.1 fabrics. The Microchip XpressConnect devices target AI data-center backplanes where channel loss at the new data rates exceeds what conventional PCB materials and via structures can support without active equalization.\nMultiphysics analysis is being folded into existing EDA sign-off loops. The Synopsys Fusion portfolio merges thermal, mechanical, and electromagnetic solvers with the place-and-route and timing engines already used for advanced nodes and multi-die assemblies, reducing the hand-off errors that appear when separate teams run independent simulations.\nMIPI SWI3S targets the growing complexity of embedded audio subsystems. The specification addresses microphone arrays, spatial speaker configurations, and AI-assisted processing inside devices that must simultaneously meet tight power, EMC, and mechanical envelopes.\nDesign debates and tensions One recurring tension is the trade-off between abstraction that speeds iteration and the loss of visibility into physical effects. Automated constraint engines catch spacing and impedance violations quickly, yet they still rely on the accuracy of the underlying stack-up and material models supplied by the designer. When those models drift, the automation simply propagates the error faster.\nA second tension appears between integrated multiphysics tools and traditional bench validation. Early thermal and electromagnetic feedback inside the layout tool shortens the loop, but it does not replace measurement of actual temperature gradients or radiated emissions once the board is populated. The data favor running both in parallel rather than substituting one for the other.\nComponent and industry news The EPC99132 evaluation board demonstrates a 100 V, 20 A GaN-based three-phase stage in a compact QFN for motor-drive use. Microchip introduced retimers explicitly positioned for PCIe 6.0 and CXL 3.1 channels in high-bandwidth installations. Efinix released the Titanium Edge FPGA family aimed at edge AI nodes that require lower power and smaller form factors than previous generations.\nResearch and technical advances No peer-reviewed technical papers or conference benchmarks appeared in the collected sources this week that meet the criteria for inclusion.\nStandards, compliance, and industry policy MIPI SWI3S is positioned to simplify audio interconnects inside consumer and industrial devices that combine multiple microphones and speakers with AI processing. The specification directly addresses electromagnetic and power constraints that grow with array size. No enforcement timeline or certification details were supplied in the source material.\nQuick Radar CRT bias procedure after replacement: The Hackaday post walks through grid and cathode voltage adjustments needed to restore proper cutoff and drive levels once a new tube is installed in an instrument. Mi Band 10 reverse engineering: The project documents the BES2700iMP SoC pinout and flash layout, enabling custom firmware development on the fitness-tracker hardware. bUniProbe wireless debugger: The open tool combines SPI, I2C, UART, CAN, GPIO, ADC, and DAC access over Wi-Fi without requiring driver installation on the host. Menlo Micro MM5800 RF switch: The SPDT micromechanical device is specified for operation to 70 GHz with 0.5 dB insertion loss and high linearity, aimed at test and quantum systems. Closing When you move a high-current GaN half-bridge or a PCIe 6.0 retimer onto a board that already carries dense digital and audio subsystems, which layout parameter usually forces the first respin: thermal spreading, return-path integrity, or power-plane resonance? The collected sources contain no traceable application-note URL, so readers are invited to compare their own stack-up assumptions against the package-level constraints described for the EPC33110 and the Microchip retimers.\nSources EDN: How automation and abstraction are transforming PCB design - https://www.edn.com/how-automation-and-abstraction-are-transforming-pcb-design/ Embedded.com: Synopsys Launches Multiphysics Fusion Solutions - https://www.embedded.com/synopsys-launches-multiphysics-fusion-solutions/ Embedded.com: MIPI SWI3S: Simplifying Embedded Audio Complexity - https://www.embedded.com/mipi-swi3s-simplifying-embedded-audio-complexity/ Hackaday: How to Bias a CRT After Installation - https://hackaday.com/2026/06/21/how-to-bias-a-crt-after-installation/ Hackaday: Hacking the Mi Band 10 Smart Band and its Bestechnic SoC - https://hackaday.com/2026/06/21/hacking-the-mi-band-10-smart-band-and-its-bestechnic-soc/ Electronics-Lab: bUniProbe - Open Source Wireless Multi-Protocol Hardware Debugger Tool - https://www.electronics-lab.com/buniprobe-open-source-wireless-multi-protocol-hardware-debugger-tool/ EDN: GaN inverter board drives compact BLDC motors - https://www.edn.com/gan-inverter-board-drives-compact-bldc-motors/ All About Circuits: Microchip Releases Data Center Retimers for High-Bandwidth Architectures - https://www.allaboutcircuits.com/news/microchip-releases-data-center-retimers-for-highbandwidth-architectures/ Electronics-Lab: Menlo Micro’s MM5800 Brings Micromechanical Switching to 70 GHz - https://www.electronics-lab.com/menlo-micros-mm5800-brings-micromechanical-switching-to-70-ghz/ ","permalink":"https://mixedsignalbrief.com/newsletter/2026-w26/","summary":"\u003cp\u003ePCB design tools and power architectures are adapting to tighter integration, faster interfaces, and multiphysics constraints that older flows no longer contain.\u003c/p\u003e\n\u003cp\u003eEngineers who have watched a differential pair fail post-layout or a return path collapse under a dense BGA already understand the core issue. Verification now arrives too late when schematic capture, layout, and manufacturing rules remain loosely coupled. Several publications this week quantify how automation layers and integrated analysis change that sequence.\u003c/p\u003e","title":"Mixed Signal Brief - Week 26, 2026"},{"content":"Automotive and data-centre high-speed interfaces are forcing new attention on compliance testing, media conversion, and package-level isolation.\nEngineers who have brought up a multi-gigabit link only to discover that the physical layer behaves differently once real cables and fault conditions appear already understand the gap between specification and silicon. This week several releases address that gap directly through compliance frameworks, media converters, and package redesigns rather than through marketing claims about speed alone.\nThe common thread is verification at the boundary between standards and hardware. Automotive SerDes, 1000BASE-T1 Ethernet, CXL memory expansion, and high-voltage SiC all require repeatable methods to confirm isolation, signal integrity, and interoperability before boards reach the integration lab. The practical question is which of these new tools actually reduce bring-up time and which simply add another layer of documentation.\nThe essentials MIPI A-PHY compliance program begins formal validation. The MIPI Alliance has opened a compliance program for its automotive SerDes specification, giving OEMs and Tier-1 suppliers a defined procedure to check conformance across multiple silicon vendors. The program targets interoperability in camera, display, and sensor links where physical-layer differences have previously required extensive custom testing.\nPEAK PAE-Media Converter supports 100/1000BASE-T1 fault insertion. The converter bridges automotive Ethernet to standard 1000BASE-T while allowing controlled fault simulation on the T1 side. This capability matters for validation teams that must reproduce cable or connector failures without building dedicated harnesses for every test case.\nCXL Type 3 memory expander bring-up guidance appears. A multi-part series outlines the sequence of firmware advertisement checks, operating-system memory mapping, and post-silicon validation steps required when adding CXL Type 3 devices to server platforms. The focus is on reconciling what the expander reports with what the kernel actually allocates.\nUHV-TO-247 package raises SiC isolation voltage. Navitas has introduced a TO-247-4-ISO package rated above 6000 V isolation for its 1200 V to 3300 V SiC MOSFETs, with more than 12 mm pin-to-pin creepage and a reflow-compatible isolated thermal pad. The design targets applications that previously required separate isolation barriers or larger module formats.\nCarbon-nanotube coating demonstrated for on-chip terahertz waveguides. Research at Skoltech shows that a nanotube layer can guide terahertz energy on silicon, addressing the regime between conventional RF traces and optical waveguides. The work remains at the materials stage but directly tackles propagation loss and confinement issues that appear once frequencies exceed 100 GHz.\nDesign debates and tensions One recurring tension is whether formal compliance programs accelerate or slow real interoperability. Proponents argue that a shared test suite removes vendor-specific interpretation of the MIPI A-PHY or 1000BASE-T1 physical layer. Skeptics note that compliance covers only the defined test points and may miss system-level interactions such as cable harness resonance or power-rail coupling that only appear after integration.\nA second tension concerns isolation versus thermal performance in high-voltage discrete packages. The new UHV-TO-247-4-ISO adds creepage and an isolated pad, yet the thermal path now depends on the quality of the reflow joint to the isolated pad rather than direct copper contact. Engineers must decide whether the added isolation margin justifies the extra thermal resistance in their particular cooling stack.\nComponent and industry news Kontron released the VX33211 3U VPX board built around the Nvidia RTX PRO 2000 Blackwell Embedded GPU for defense and aerospace edge workloads. Congatec received IEC 62443-4-1:2018 certification covering the full development lifecycle of its embedded modules and stacks. Both items affect teams already working inside VPX or COM Express ecosystems rather than introducing new interface standards.\nResearch and technical advances The EDN series on CXL Type 3 expanders supplies concrete bring-up checklists for firmware and kernel teams rather than abstract architecture descriptions. The carbon-nanotube waveguide paper quantifies guidance at terahertz frequencies on silicon, a step beyond simulation-only results previously available for on-chip millimetre-wave structures.\nStandards, compliance, and industry policy The MIPI A-PHY compliance program is the first formal framework for an automotive SerDes standard. Teams adopting A-PHY devices can now reference a common test specification instead of negotiating test plans individually with each silicon supplier. The IEC 62443-4-1 certification obtained by Congatec applies to development processes rather than to individual products, so its immediate effect appears in supplier audit questionnaires rather than in board-level design rules.\nQuick Radar Arduino echo project: A simple ATmega328-based audio platform with PCB layout files and code demonstrates basic signal-path bring-up on a two-layer board. Qorvo SOI switch family: Three new switches spanning 50 MHz to 10 GHz target 5G radio front-ends where component count reduction directly affects board area. Antenna-first IoT layout advice: Early placement of antennas before final routing is presented as necessary once multiple bands and shrinking enclosures are combined. Magnetometer-based positioning: Work on magnetic-map absolute positioning offers an alternative when GNSS is unavailable for airborne or underwater platforms. Closing How do you currently verify that a media converter or SerDes link reproduces the exact fault conditions specified in the standard without introducing additional parasitics from the test fixture itself?\nCompare the thermal resistance path through the isolated pad of the new UHV-TO-247-4-ISO package against a conventional TO-247 on your existing heatsink stack-up before committing to layout changes.\nSources Embedded.com: Congatec Earns IEC 62443-4-1 for Embedded Development Processes - https://www.embedded.com/congatec-earns-iec-62443-4-1-for-embedded-development-processes/ Embedded.com: MIPI Launches A-PHY Compliance Program for Automotive SerDes Devices - https://www.embedded.com/mipi-launches-a-phy-compliance-program-for-automotive-serdes-devices/ EDN: Bring-up and testing of systems with CXL Type 3 memory expanders - https://www.edn.com/bring-up-and-testing-of-systems-with-cxl-type-3-memory-expanders/ Embedded.com: Kontron Introduces VX33211 3U VPX GPU Board - https://www.embedded.com/kontron-introduces-vx33211-3u-vpx-gpu-board/ EDN: TO-247 SiC package boosts high-voltage isolation - https://www.edn.com/to-247-sic-package-boosts-high-voltage-isolation/ All About Circuits: The Voice Echo: An Arduino Audio Project - https://www.allaboutcircuits.com/projects/the-voice-echo-an-arduino-audio-project/ EDN: Carbon nanotube coating creates on-chip terahertz waveguides - https://www.edn.com/carbon-nanotube-coating-creates-on-chip-terahertz-waveguides/ EE Times: PEAK Goes Automotive Ethernet: PAE-Media Converter connects 100/1000BASE-T1 with Standard Ethernet - https://www.eetimes.com/peak-goes-automotive-ethernet-pae-media-converter-connects-100-1000base-t1-with-standard-ethernet/ ","permalink":"https://mixedsignalbrief.com/newsletter/2026-w25/","summary":"\u003cp\u003eAutomotive and data-centre high-speed interfaces are forcing new attention on compliance testing, media conversion, and package-level isolation.\u003c/p\u003e\n\u003cp\u003eEngineers who have brought up a multi-gigabit link only to discover that the physical layer behaves differently once real cables and fault conditions appear already understand the gap between specification and silicon. This week several releases address that gap directly through compliance frameworks, media converters, and package redesigns rather than through marketing claims about speed alone.\u003c/p\u003e","title":"Mixed Signal Brief - Week 25, 2026"},{"content":"Power delivery integration and substrate choices are tightening constraints on automotive chargers, RF devices, and memory interfaces.\nEngineers who have laid out a buck converter on a two-layer board while trying to meet USB Power Delivery transient specs already know how quickly input voltage range and thermal paths interact. This week several component announcements and roadmaps highlight the same interaction at higher power levels and different frequency bands. The common thread is that integration of control functions and changes in substrate technology are being used to manage parasitic effects and board-level constraints rather than simply increasing switching frequency or die size.\nThe practical implication is that next board revisions for in-vehicle chargers or small-cell radios will need to re-examine both layout assumptions and thermal vias once the new parts are substituted. Memory roadmaps add a parallel pressure on power integrity as LPDDR6 moves into data-center adjacent roles. These developments reward engineers who treat package parasitics and controller integration as first-order design variables rather than after-the-fact fixes.\nThe essentials Automotive buck controller merges PD source logic A synchronous buck controller from Diodes integrates a USB Type-C PD 3.1 source controller that operates from a 4 V to 36 V input and supports extended power range up to 28 V. The combination removes a separate PD controller and its associated board area while still allowing programmable power supply and adjustable voltage supply modes. Layout must still account for the wide input range and the thermal paths required to sustain 140 W continuous delivery.\nGaN-on-silicon targets RF parasitic reduction A GaN-on-silicon process development aims to lower parasitic losses that have historically kept GaN RF devices on silicon-carbide substrates. The approach keeps the cost advantage of silicon while addressing the substrate-related contributions to loss at RF frequencies. Device engineers will still need measured S-parameter data under the intended bias and temperature conditions before committing to a production layout.\nLPDDR6 roadmap extends into data-center use JEDEC’s upcoming LPDDR6 specification is adding features that support the memory’s growing presence in AI data-center environments. The changes address bandwidth and power-efficiency requirements that differ from the original mobile-centric use cases. Board designers will need updated power-distribution network targets once the final timing and voltage specifications are released.\nLegacy 1N4148 diode remains a reference part Registered at JEDEC in 1968 as a tighter-specification successor to the 1N914, the 1N4148 continues to appear in new designs because its forward-recovery and capacitance characteristics are well characterized across decades of production. Its persistence illustrates how a component with stable, published parameters can outlast marketing cycles for newer parts.\nBiometric Click board combines multiple sensing modalities The Mikroe Life Metrics Click integrates photoplethysmography, electrocardiogram, bioelectrical impedance, and electrodermal activity channels on one board for wearable and biomedical prototyping. The combination allows direct comparison of signal integrity across modalities on the same PCB stack-up before committing to a custom layout.\nDesign debates and tensions GaN-on-silicon versus GaN-on-silicon-carbide remains an active tradeoff discussion. Silicon-carbide substrates have provided lower RF losses and better thermal conductivity, yet they carry higher material cost and limited wafer diameter. The new silicon-based process claims to close enough of the parasitic gap to change the economics for volume RF applications, but engineers still require side-by-side efficiency and linearity data at the target frequency and power level before accepting the substrate change. The deciding factor will be whether measured insertion loss and thermal resistance meet the link budget once the device is mounted on a production PCB.\nComponent and industry news The Diodes APK43070Q buck controller targets single- and multi-port automotive USB charging with integrated PD 3.1 source control. LPDDR6 development is explicitly addressing data-center memory needs in addition to mobile applications. The 1N4148 continues in production with no announced end-of-life. The Mikroe Life Metrics Click provides a compact platform for multi-parameter biometric evaluation.\nResearch and technical advances No peer-reviewed papers or conference results with quantitative hardware benchmarks were present in the collected sources this week.\nStandards, compliance, and industry policy JEDEC continues work on the LPDDR6 update. The specification changes are intended to support higher bandwidth and improved power efficiency in non-mobile environments. System designers should review the draft timing parameters and voltage tolerances once they become available to update power-distribution network simulations ahead of the next board spin.\nQuick Radar Product recall guide: A guide outlines structured recall processes for small and midsize electronics manufacturers facing field failures. Mini-fab sales: InchFab is offering compact fabrication systems to universities and pharmaceutical firms seeking in-house semiconductor capability. AI library characterization tool: Siemens released software that combines predictive AI with a SPICE engine to accelerate standard-cell library characterization. CubeSat reflectarray antenna: A 64-gram origami reflectarray demonstrated 20 Mbps circularly polarized links from low-Earth orbit. Satellite IoT transition: Current satellite IoT operators are evaluating spectrum and protocol strategies ahead of 6G NB-IoT non-terrestrial network deployment. Quantum control hardware: Quantum computing systems continue to require substantial classical electronics for calibration and decoding. Closing When substituting an integrated automotive USB PD controller for a discrete buck-plus-PD solution, how do you verify that the combined thermal resistance and transient response still meet the original 140 W specification across the full 4 V to 36 V input range on your existing PCB copper area?\nCompare the measured efficiency curves of the new GaN-on-silicon devices against your current GaN-on-SiC reference design at the same bias point and frequency before updating the bill of materials.\nSources EDN: Buck controller streamlines in-vehicle USB charging - https://www.edn.com/buck-controller-streamlines-in-vehicle-usb-charging/ EE Times: LPDDR6 Roadmap Leads to the Data Center - https://www.eetimes.com/lpddr6-roadmap-leads-to-the-data-center/ All About Circuits: The 1N4148: The Signal Diode That Ended Up Everywhere - https://www.allaboutcircuits.com/news/the-1n4148-the-signal-diode-that-ended-up-everywhere/ Embedded.com: Mikroe Launches Life Click Board for Vital Sign Monitoring - https://www.embedded.com/mikroe-launches-life-click-board-for-vital-sign-monitoring/ EDN: The RF-ready GaN-on-silicon with lower parasitic losses - https://www.edn.com/the-rf-ready-gan-on-silicon-with-lower-parasitic-losses/ ","permalink":"https://mixedsignalbrief.com/newsletter/2026-w24/","summary":"\u003cp\u003ePower delivery integration and substrate choices are tightening constraints on automotive chargers, RF devices, and memory interfaces.\u003c/p\u003e\n\u003cp\u003eEngineers who have laid out a buck converter on a two-layer board while trying to meet USB Power Delivery transient specs already know how quickly input voltage range and thermal paths interact. This week several component announcements and roadmaps highlight the same interaction at higher power levels and different frequency bands. The common thread is that integration of control functions and changes in substrate technology are being used to manage parasitic effects and board-level constraints rather than simply increasing switching frequency or die size.\u003c/p\u003e","title":"Mixed Signal Brief - Week 24, 2026"},{"content":"Integrated local power conversion is easing thermal and space constraints in automotive lighting and high-voltage infrastructure\nEngineers who have routed an external buck converter next to an LED driver know the layout penalty: extra copper area, additional vias, and a separate thermal path that must be managed on an already crowded automotive PCB. This week two separate releases show the same engineering response: move the conversion stage inside the controller package so that the local supply voltage can be generated at the point of load.\nThe practical result is fewer external components, lower total dissipation, and simpler thermal budgeting. The same pattern appears in high-voltage SiC modules that collapse multi-stage topologies into two-level designs. The common thread is that package-level integration is now being used to shift the thermal and layout problem from the board designer back to the silicon definition.\nThe essentials LIN RGB controller adds local supply. The MLX81119 integrates a 1 A DC/DC converter that produces a programmable LED supply between 2.5 V and 6 V directly on the same die as the 18-channel driver. This removes the external buck stage that previously contributed both heat and board area in dashboard, door-panel, and ambient-lighting applications.\nPower dissipation moves inside the package. By generating the optimised local voltage at the controller rather than upstream, the design reduces the voltage drop across the LED strings and therefore the power that must be sunk as heat on the PCB. The approach directly addresses the thermal density increase that accompanies higher electronic content in modern vehicles.\nLIN interface remains the control backbone. The device retains the LIN bus connection while embedding the power stage, allowing existing automotive lighting networks to adopt the part without changes to the communication layer or the addition of a second power rail.\nSiC modules target high-voltage simplification. Two 3.3 kV Wolfspeed modules, one half-bridge rated above 800 A and one full-bridge rated at 100 A, are intended for DC-link voltages of 2 kV and higher. The modules support direct use of two-level topologies in energy infrastructure and AI data-centre power systems, removing intermediate conversion stages that would otherwise be required.\nBaseplate and baseplate-less options address thermal paths. The availability of both module styles lets designers trade mechanical mounting and cooling surface area against current rating, giving concrete choices when the limiting factor is heat extraction rather than switching loss.\nDesign debates and tensions Integration of the DC/DC stage inside the LED controller trades flexibility for simplicity. An external converter can be sized and placed independently, but it adds components and thermal interfaces. The integrated approach fixes the converter rating at 1 A and places the thermal load inside the controller package, which may constrain maximum LED current or require careful copper pour design beneath the device. Data on which approach yields lower total system dissipation under realistic automotive ambient conditions is not yet public.\nComponent and industry news The MLX81119 targets automotive RGB lighting nodes where space and heat are both constrained. The Wolfspeed HAB900C33LM4 and IBB020A33GM4 modules address 3.3 kV infrastructure designs that can now use simpler two-level topologies.\nResearch and technical advances No new academic or benchmark results with quantitative hardware data were released this week that fit the power-integration thread.\nStandards, compliance, and industry policy No new standards documents or regulatory changes affecting power or automotive lighting interfaces were issued this week.\nQuick Radar AI silicon data movement: Network-on-chip architectures are becoming central to observability in AI SoCs, but the discussion remains at the architectural level without new measurement techniques. Nordic AI-assisted IoT framework: The platform adds workflow assistance across hardware, firmware, and cloud, yet offers no new hardware specifications. University quantum computer acquisition: The University of Saskatchewan has installed a full-stack open-architecture system for cross-domain research; no device-level electronics details are provided. SSD controller for KVCache: Silicon Motion released the SM2524XT PCIe Gen5 DRAMless controller aimed at AI inference workloads. Automotive GNSS modules: u-blox introduced the ZED-X20K and ZED-A20K for ADAS L2+ through L4 positioning with functional-safety support. Gold-plated tactile switches: Contact-material choices are discussed for signal integrity and lifecycle in high-end boards, without new part numbers. 4D imaging radar: bitsensing announced the AIR4D sensor for autonomous-vehicle point-cloud and Doppler data. Closing When the DC/DC converter is placed inside the LED controller, what copper area and via pattern under the package are actually required to keep junction temperature within limits at the maximum programmable output voltage? A side-by-side thermal measurement on the same board with and without the integrated stage would give designers the data they need for the next revision.\nSources Embedded.com: Melexis Launches Automotive 18-Channel LIN RGB LED Controller - https://www.embedded.com/melexis-launches-automotive-18-channel-lin-rgb-led-controller/ EE Times: Canada’s University of Saskatchewan Acquires Quantum Computer - https://www.eetimes.com/canada-university-of-saskatchewan-acquires-quantum-computer/ Circuit Cellar: bitsensing Unveils New 4D Imaging Radar for Autonomous Vehicles, Designed to Accelerate Route To Commercialization - https://circuitcellar.com/newsletter/bitsensing-unveils-4d-imaging-radar-for-autonomous-vehicles/ ","permalink":"https://mixedsignalbrief.com/newsletter/2026-w23/","summary":"\u003cp\u003eIntegrated local power conversion is easing thermal and space constraints in automotive lighting and high-voltage infrastructure\u003c/p\u003e\n\u003cp\u003eEngineers who have routed an external buck converter next to an LED driver know the layout penalty: extra copper area, additional vias, and a separate thermal path that must be managed on an already crowded automotive PCB. This week two separate releases show the same engineering response: move the conversion stage inside the controller package so that the local supply voltage can be generated at the point of load.\u003c/p\u003e","title":"Mixed Signal Brief - Week 23, 2026"},{"content":"Power delivery integration is tightening the coupling between local regulation, thermal layout, and interface standards in mobile and automotive designs.\nEngineers who have routed a high-current Vcore rail only to discover that the remote sense point sits too far from the load already understand the core constraint. When the processor or LED matrix sits millimeters from the power stage, every additional millimeter of copper trace adds both voltage drop and thermal resistance. This week several component releases make that constraint explicit by moving regulation onto the same package or board as the load.\nThe pattern appears across mobile processors, automotive lighting, and high-speed serial links. In each case, the design goal is the same: reduce the distance between the final regulation stage and the consuming silicon or LEDs while still meeting the transient, EMI, and safety requirements of the larger system. The practical result is that board-level power architecture decisions now intersect directly with package choice and interface timing budgets.\nFive distinct consequences follow from this shift. They affect controller selection, LED driver architecture, PHY security features, test equipment roadmaps, and power-device participation in larger vehicle programs.\nThe essentials Multiphase controllers target mobile Vcore rails. Three new digital multiphase controllers from AOS pair with the vendor\u0026rsquo;s DrMOS and Smart Power Stage devices to support Intel IMVP9.3 power delivery for Panther Lake and Wildcat Lake processors. The architecture places the final regulation stage close to the processor die, shortening the high-current path that previously limited transient response on two-layer or thin-copper mobile boards.\nLIN RGB controller adds local supply regulation. The MLX81119 integrates an 18-channel LED driver with a 1 A DC/DC converter that generates an optimized local supply for the LEDs. By eliminating the external regulator that would otherwise sit between the vehicle 12 V rail and the LED string, the part reduces both board area and the number of connections that must survive automotive temperature cycling and vibration.\nMatrix LED driver supports dynamic exterior lighting. The IS32FL3776 provides 36 constant-current channels at 60 mA each, allowing software-defined matrices up to 36 by 6. The constant-current architecture removes the need for per-channel ballast resistors, but it still requires the PCB designer to manage the combined thermal load of 216 individually addressable LEDs within the same footprint that previously held simpler signal lamps.\nSingle-pair Ethernet PHYs embed security at the physical layer. Microchip\u0026rsquo;s LAN878x and LAN888x families add IEEE 802.1AE-2018 frame encryption and TSN support to 100/1000BASE-T1 transceivers. The security functions sit inside the same device that already handles the 1000BASE-T1 physical layer, so the additional latency and power cost appear directly in the PHY rather than in a separate processor or FPGA.\nPCIe 7.0 test ecosystem begins to close coverage gaps. New automated test applications, low-jitter clock generators, and protocol analyzers address the measurement requirements that appear once data rates move beyond the reach of equipment calibrated for PCIe 6.0. The timing and jitter specifications now drive both instrument selection and board-level reference-clock routing decisions.\nDesign debates and tensions One recurring tension is whether regulation should move inside the LED or PHY package or remain on a separate power-management IC. On-package regulation shortens the critical current path and reduces the number of high-current vias, yet it also concentrates heat in a smaller area and limits the designer\u0026rsquo;s ability to choose the optimum inductor or capacitor technology. Discrete regulation preserves layout flexibility but adds interconnect parasitics that become measurable once load-step slew rates exceed several amperes per microsecond.\nComponent and industry news CSA Catapult is contributing SiC device and module expertise to project SONATA, which is developing an on-aircraft electric taxiing system. The involvement signals that SiC power stages are moving from aerospace demonstrators into programs that must satisfy both performance and certification requirements for ground operations.\nResearch and technical advances A millimeter-wave backscatter link demonstrated Gbps data rates while harvesting sufficient power from the incident GHz carrier to operate without a local battery. The approach combines a passive lens with a modulated reflector, showing that the same RF energy used for communication can also close the power budget when the link distance and antenna gain are chosen appropriately.\nStandards, compliance, and industry policy PCIe 7.0 test and timing tools are appearing as the specification moves from draft into early silicon validation. The new equipment targets the jitter and eye-mask requirements that appear at the next doubling of per-lane bandwidth, directly affecting reference-clock distribution and PCB material choices on server and accelerator boards.\nQuick Radar VAR-SMARC-MX95 SoM: A new NXP i.MX95-based module joins the SMARC family for edge AI and industrial IoT designs that require heterogeneous cores and retained pin compatibility with earlier modules. ETH WIZ 3 Click: The add-on board supplies both Ethernet MAC/PHY and local processing for IoT gateways and industrial controllers that need network connectivity without a full carrier-board redesign. MATLAB and Simulink Renesas support: New hardware packages allow direct deployment of control algorithms to RA6T2 and RH850 microcontrollers for automotive and industrial motor-drive applications. Osptek 4-inch IPS display: The 720 by 720 capacitive touchscreen module uses a MIPI interface and ST7703 driver for embedded human-machine interface panels. Closing When you place the final regulation stage within millimeters of a 100 W processor or a 200-LED matrix, which thermal and transient measurements become the binding constraints on your next board revision? Compare the measured voltage droop at the die or LED anode with the value predicted by the controller vendor\u0026rsquo;s reference layout, then decide whether the remaining margin justifies moving to a four-layer or thicker-copper stack-up.\nSources EDN: Multiphase controllers optimize mobile Vcore power - https://www.edn.com/multiphase-controllers-optimize-mobile-vcore-power/ Electronics Weekly: MLX81119 integrates on-chip DC/DC power with LIN RGB automotive lighting - https://www.electronicsweekly.com/news/products/power-supplies/mlx81119-integrates-on-chip-dc-dc-power-with-lin-rgb-automotive-lighting-2026-05/ EDN: LED driver animates exterior vehicle lighting - https://www.edn.com/led-driver-animates-exterior-vehicle-lighting/ All About Circuits: Microchip’s 100/1000BASE-T1 SPE PHYs Pack Security and Safety Features - https://www.allaboutcircuits.com/news/microchip-rolls-out-lan878x-and-lan888x-single-pair-ethernet-phys/ All About Circuits: PCIe 7.0 Roundup: Test and Timing Tools Emerge as Ecosystem Takes Shape - https://www.allaboutcircuits.com/news/pcie-7.0-roundup-test-and-timing-tools-emerge-as-ecosystem-takes-shape/ Electronics Weekly: CSA Catapult joins project SONATA for aircraft taxiing system - https://www.electronicsweekly.com/news/business/csa-catapult-joins-project-sonata-for-aircraft-taxiing-system-2026-05/ Embedded.com: Variscite Expands its VAR-SMARC SoM Portfolio - https://www.embedded.com/variscite-expands-its-var-smarc-som-portfolio/ Embedded.com: Mikroe Expands Click Board Portfolio with Ethernet IoT Solution - https://www.embedded.com/mikroe-expands-click-board-portfolio-with-ethernet-iot-solution/ ","permalink":"https://mixedsignalbrief.com/newsletter/2026-w22/","summary":"\u003cp\u003ePower delivery integration is tightening the coupling between local regulation, thermal layout, and interface standards in mobile and automotive designs.\u003c/p\u003e\n\u003cp\u003eEngineers who have routed a high-current Vcore rail only to discover that the remote sense point sits too far from the load already understand the core constraint. When the processor or LED matrix sits millimeters from the power stage, every additional millimeter of copper trace adds both voltage drop and thermal resistance. This week several component releases make that constraint explicit by moving regulation onto the same package or board as the load.\u003c/p\u003e","title":"Mixed Signal Brief - Week 22, 2026"},{"content":"Power delivery integration is tightening constraints on layout, thermal paths, and local regulation across mobile, automotive, and high-speed platforms.\nEngineers who have routed a high-current Vcore rail on a thin mobile PCB already know that controller choice directly sets the number of phases, the copper area required, and the allowable transient droop. This week several releases and roadmaps converge on the same practical question: how much regulation and protection can be moved on-chip or into the same package without violating thermal or EMC limits.\nThe pattern is clearest in automotive and mobile designs where multiple high-current LED strings, processor cores, and zonal networks must share board real estate. Integrated DC/DC stages reduce external inductor count but shift the thermal problem to the controller package and the PCB copper directly beneath it. At the same time, longer-term process roadmaps signal that logic density gains after 2033 will depend on new transistor architectures whose primary benefit is lower power density rather than raw speed.\nThese developments force designers to re-examine where the boundary between power stage and digital load should sit on the next board revision.\nThe essentials Multiphase controllers target mobile Vcore rails. Three new digital multiphase controllers address Intel IMVP9.3 power delivery when paired with matching DrMOS and Smart Power Stage devices. The architecture supports the higher phase counts needed for Panther Lake and Wildcat Lake processors while keeping the controller footprint compatible with existing mobile layouts.\nLIN RGB controller moves regulation on-chip. The MLX81119 combines an 18-channel LED driver with a 1 A DC/DC converter that generates a local optimised supply for the LEDs. This removes the need for a separate regulator stage in LIN-based automotive lighting nodes and places the thermal load of the converter inside the same package that already handles the LED current paths.\nSiC power expertise enters aircraft taxiing project. CSA Catapult will contribute silicon-carbide device knowledge to project SONATA, which is developing an on-aircraft electric taxiing system. The involvement highlights the continuing shift toward SiC in high-reliability traction and actuation supplies where efficiency at partial load and high-temperature operation matter more than peak switching frequency.\nMatrix LED driver supports dynamic exterior lighting. The IS32FL3776 provides 36 constant-current channels at 60 mA each, enabling software-defined exterior lighting matrices up to 36 by 6. Individual addressing of 216 LEDs requires careful PCB current return paths and local decoupling to avoid visible flicker or EMC issues during rapid pattern changes.\nRoadmap projects CFET transition for power-limited scaling. Imec’s updated semiconductor technology outlook places the move to CFET logic at 2033, followed by atomic-layer 2D channel materials aimed at further power-efficiency gains. The timeline underscores that future density improvements will be gated by thermal and supply-current limits rather than lithography alone.\nDesign debates and tensions One recurring tension is whether to integrate the DC/DC converter with the LED or interface controller, as in the MLX81119, or keep regulation external. Integration reduces component count and interconnect inductance, yet it concentrates heat in a single package and forces the PCB designer to allocate copper area and vias under that package. External regulation spreads the thermal load but adds board space and parasitic inductance that can affect LED current accuracy at high dimming frequencies. Available device information does not yet quantify the exact copper-area or via-count trade-offs for either approach.\nComponent and industry news Microchip introduced 100/1000BASE-T1 single-pair Ethernet PHY families that add IEEE 802.1AE-2018 frame security and TSN support for zonal automotive and industrial networks. Variscite added an NXP i.MX95-based module to its SMARC portfolio aimed at edge AI and industrial IoT. Both releases emphasise interface security and real-time features rather than raw power metrics.\nResearch and technical advances Imec’s long-term roadmap to 2041 frames the CFET architectural change as the next major step after gate-all-around nanosheets, with the explicit goal of containing power density. The projection supplies a concrete timeline against which power-architecture decisions for products shipping after 2030 can be benchmarked.\nStandards, compliance, and industry policy Test and timing tools for PCIe 7.0 are appearing as the ecosystem prepares for the next data-rate step. Automated test applications, low-jitter clock generators, and protocol analysers address measurement gaps that appear once signalling moves beyond the validation methods established for PCIe 6.0. Designers working on early platforms will need to verify that existing test fixtures and probe points remain adequate or plan for new fixturing.\nQuick Radar PCB layout discussion: Impedance of analog signal sources determines whether star grounding or local reference planes are required on mixed-signal boards. mmWave insect classification: Micro-Doppler signatures from millimetre-wave radar distinguish bee from wasp wingbeats, illustrating a non-contact sensing technique applicable to other vibrating mechanical systems. ETH WIZ 3 Click: The board adds Ethernet connectivity and onboard processing for IoT gateways and industrial controllers through a standard Click interface. Hand-layout PCB map: A California East Bay map rendered entirely in copper demonstrates how top-side traces can serve both electrical and visual functions when current requirements are modest. Closing When selecting between an integrated DC/DC LED controller and a discrete regulator plus driver, what measurement on the bench first reveals whether the integrated solution will meet the thermal budget on your target PCB stack-up? Compare the two approaches on a four-layer board with identical LED load and ambient conditions, recording case temperature rise and supply current at the highest expected dimming frequency.\nSources EDN: Multiphase controllers optimize mobile Vcore power - https://www.edn.com/multiphase-controllers-optimize-mobile-vcore-power/ Electronics Weekly: MLX81119 integrates on-chip DC/DC power with LIN RGB automotive lighting - https://www.electronicsweekly.com/news/products/power-supplies/mlx81119-integrates-on-chip-dc-dc-power-with-lin-rgb-automotive-lighting-2026-05/ Electronics Weekly: CSA Catapult joins project SONATA for aircraft taxiing system - https://www.electronicsweekly.com/news/business/csa-catapult-joins-project-sonata-for-aircraft-taxiing-system-2026-05/ EDN: LED driver animates exterior vehicle lighting - https://www.edn.com/led-driver-animates-exterior-vehicle-lighting/ IEEE Spectrum: Semiconductor technology roadmap to 2041 - https://spectrum.ieee.org/semiconductor-technology-roadmap All About Circuits: Microchip’s 100/1000BASE-T1 SPE PHYs Pack Security and Safety Features - https://www.allaboutcircuits.com/news/microchip-rolls-out-lan878x-and-lan888x-single-pair-ethernet-phys/ Embedded.com: Variscite Expands its VAR-SMARC SoM Portfolio - https://www.embedded.com/variscite-expands-its-var-smarc-som-portfolio/ All About Circuits: PCIe 7.0 Roundup: Test and Timing Tools Emerge as Ecosystem Takes Shape - https://www.allaboutcircuits.com/news/pcie-7.0-roundup-test-and-timing-tools-emerge-as-ecosystem-takes-shape/ Embedded.com: Mikroe Expands Click Board Portfolio with Ethernet IoT Solution - https://www.embedded.com/mikroe-expands-click-board-portfolio-with-ethernet-iot-solution/ ","permalink":"https://mixedsignalbrief.com/newsletter/2026-w21/","summary":"\u003cp\u003ePower delivery integration is tightening constraints on layout, thermal paths, and local regulation across mobile, automotive, and high-speed platforms.\u003c/p\u003e\n\u003cp\u003eEngineers who have routed a high-current Vcore rail on a thin mobile PCB already know that controller choice directly sets the number of phases, the copper area required, and the allowable transient droop. This week several releases and roadmaps converge on the same practical question: how much regulation and protection can be moved on-chip or into the same package without violating thermal or EMC limits.\u003c/p\u003e","title":"Mixed Signal Brief - Week 21, 2026"},{"content":"Mixed Signal Brief is a weekly electronics engineering newsletter for hardware engineers. Every Monday, a concise brief on what matters in electronics design — no gadgets, no hype, no noise.\nWhat is Mixed Signal Brief Electronics engineering moves fast. New components, updated standards, design techniques, silicon process nodes, EMC regulations, test methods, power architectures and embedded interfaces — all at once, across dozens of sources with very uneven quality. Separating what matters from vendor marketing is a job in itself.\nMixed Signal Brief does that job for you. Every week we monitor the most relevant sources in electronics engineering — technical publications, application notes, standards bodies, design communities and engineering blogs — and distil it into a curated brief with editorial context and practical engineering relevance.\nWhat you will find every Monday Opening note — A technically grounded take on the most relevant development of the week.\nThe five signals that matter — The most important news and developments explained with engineering context. No empty headlines.\nComponent and semiconductor watch — New parts, supply chain developments and silicon news that affect real designs.\nCircuit design and signal chain — Analog, mixed-signal and RF design: op-amps, ADC/DAC, filters, sensor front-ends, signal integrity.\nEmbedded hardware and digital interfaces — Microcontrollers, FPGAs, buses, timing, protocols and firmware-level hardware topics.\nPower, thermal and reliability — DC/DC converters, LDOs, GaN, SiC, thermal design, efficiency and reliability.\nPCB design, signal integrity and EMC — Layout, grounding, impedance, decoupling, EMI/EMC and bring-up practice.\nTest bench note — Oscilloscopes, logic analysers, power analysers, calibration and measurement practice.\nEngineering takeaway — One practical, concrete thing an engineer can apply this week.\nRecommended reads — Datasheets, application notes, papers and resources worth your time.\nHow Mixed Signal Brief is made Mixed Signal Brief is generated by an AI. Reviewed by another AI.\nEvery week, a fully automated system monitors the most relevant electronics engineering sources, synthesises what matters and publishes the result. A first AI drafts the brief; a second reviews it editorially. What you read is the direct output of that pipeline.\nWhy do we say this openly? Because a newsletter about engineering that used AI without disclosing it would be, at minimum, inconsistent. And because we believe the best way to demonstrate what this technology can do is to use it well, in plain sight.\nEditorial philosophy Technical, not academic. Written for engineers who design, debug, validate and integrate electronics — not for researchers writing papers.\nEngineering-focused, not gadget-focused. We cover circuits, components and design practice. We do not cover smartphones, laptops or consumer electronics unless there is a real hardware engineering angle.\nSceptical of vendor hype. Product claims are clearly labelled as such. Independent technical validation is always preferred over press releases.\nPrimary sources first. Datasheets, application notes, standards documents and original technical analyses take priority over secondary coverage.\nGlobal scope. Electronics engineering is a global discipline. Sources, components and design challenges come from everywhere.\nFree subscription Receive Mixed Signal Brief every Monday in your inbox. No cost, no spam, no small print.\n👉 Subscribe on Buttondown\nContact Suggestions, corrections or a source you think we should monitor? We welcome feedback.\nWrite to us at mixedsignalbrief@proton.me or via X at @MixedSigBrief.\n","permalink":"https://mixedsignalbrief.com/about/","summary":"\u003cp\u003e\u003cstrong\u003eMixed Signal Brief\u003c/strong\u003e is a weekly electronics engineering newsletter for hardware engineers. Every Monday, a concise brief on what matters in electronics design — no gadgets, no hype, no noise.\u003c/p\u003e\n\u003ch2 id=\"what-is-mixed-signal-brief\"\u003eWhat is Mixed Signal Brief\u003c/h2\u003e\n\u003cp\u003eElectronics engineering moves fast. New components, updated standards, design techniques, silicon process nodes, EMC regulations, test methods, power architectures and embedded interfaces — all at once, across dozens of sources with very uneven quality. Separating what matters from vendor marketing is a job in itself.\u003c/p\u003e","title":"About Mixed Signal Brief"}]