Power delivery and thermal constraints now dominate layout and component choices in AI servers, automotive systems, and high-density converters.

Engineers who have traced a 50 mV drop on a power plane back to a single via under a MOSFET already understand the stakes. This week several releases converge on the same practical problem: delivering clean power at higher densities while keeping temperatures and noise within limits. The common thread is not new silicon alone but the interaction between package construction, measurement technique, and board-level layout.

Stacked-die MOSFETs, hybrid capacitors, and isolated current probes each address one slice of that interaction. AI server SSDs and automotive PMICs show where the same constraints appear at system level. The result is a set of design decisions that now start with copper area, via count, and probe bandwidth rather than headline efficiency numbers.

The essentials

Stacked-die half-bridge raises power density limits. A vertically integrated DFN6x5 package places high-side and low-side MOSFETs in the same footprint, cutting board area compared with two discrete DFN5x6 parts. The approach targets megawatt-scale AI power conversion and compact motor drives where PCB real estate is already budgeted to the square millimetre.

Wideband shunts extend isolated current measurement bandwidth. The TICS series pairs with existing IsoVu probes to give higher-frequency content without sacrificing galvanic isolation. Accurate capture of fast switching edges now depends on both probe selection and the layout of the shunt itself.

Hybrid capacitors address automotive power smoothing. The HVX and HTX series meet AEC-Q200 requirements for conductive-polymer aluminium electrolytics used in steering and Advanced Driver Assistance Systems (ADAS) supplies. Their role is noise suppression and voltage stabilisation where ripple current and temperature cycling are both high.

Enterprise SSD performance directly affects AI server power budgets. The PM1763 drive reaches 28,400 MB/s sequential read on a PCIe 6.0 interface with a 4 nm controller. Higher throughput shortens active time but raises instantaneous current demand on the backplane, shifting thermal design focus to the SSD cage and its airflow.

Automotive PMIC targets brake-by-wire functional safety. The A81415 integrates regulation and monitoring functions rated to Automotive Safety Integrity Level D (ASIL-D). Its value lies in reducing discrete component count while satisfying the fault-coverage requirements that brake systems now carry.

Design debates and tensions

Measurement bandwidth versus isolation remains unsettled. Wideband shunts improve edge fidelity but still require careful return-path layout to avoid coupling into adjacent signals. Some teams accept lower bandwidth differential probes and rely on post-processing; others insist on full galvanic isolation even when it forces extra board layers. The data favour the isolated path once common-mode voltages exceed a few hundred volts, yet the layout penalty is real.

Component and industry news

The AOS AmpStack DFN6x5 half-bridge targets high-density DC-DC stages. Taiyo Yuden’s 46-member HVX/HTX capacitor family is qualified for automotive power rails. Allegro’s A81415 PMIC is positioned for brake-by-wire modules. Samsung’s PM1763 SSD family offers 4 TB to 16 TB capacities on PCIe 6.0.

Research and technical advances

Presentations at Leti Innovation Days 2026 framed the next semiconductor bottleneck as efficient electricity delivery rather than raw transistor density. The discussion centred on co-optimisation of system architecture and process technology to keep total energy per operation from rising with each new AI workload. Voyager spacecraft power management continues to illustrate extreme long-duration constraints where every microwatt and every thermal path must be accounted for decades in advance.

Standards, compliance, and industry policy

No new standards releases appeared this week that directly alter qualification flows. Existing AEC-Q200 and ISO 26262 requirements continue to drive the capacitor and PMIC selections noted above.

Quick Radar

  • PCIe Gen2/Gen3 analog MUX layout: A concrete board-level implementation shows routing and termination choices for a 1:2 switch without introducing excessive insertion loss.
  • Microchip MPLAB tools now free: Unlimited licences remove cost barriers for teams using the XC compilers and machine-learning suite on embedded targets.
  • Advantech SMARC module on Qualcomm Dragonwing: The AOM-6741 provides an industrial edge-AI platform with defined thermal and mechanical interfaces.
  • Renesas acquisition of Pictorus: Cloud-based behavioural modelling is being folded into the Altium-linked Renesas 365 flow to shorten control-algorithm iteration.

Closing

How many square millimetres of copper pour and how many vias per amp do you budget under a stacked half-bridge before you accept the next temperature rise? If a traceable available device information or reference design URL had been supplied this week, it would appear here; instead, the practical question is whether your current via pattern still meets the same current density once the package changes from two discrete MOSFETs to one stacked part.

Sources

  1. EDN: Stacked-die half-bridge boosts MOSFET power density - https://www.edn.com/stacked-die-half-bridge-boosts-mosfet-power-density/
  2. Power Electronics News: Power Corner: THDP0400 and TICS Wideband Shunts, Explained - https://www.powerelectronicsnews.com/power-corner-thdp0400-and-tics-wideband-shunts-explained/
  3. EDN: Enterprise SSD accelerates AI server data transfer - https://www.edn.com/enterprise-ssd-accelerates-ai-server-data-transfer/
  4. Power Electronics News: New Allegro A81415 PMIC Simplifies Brake-by-Wire Systems - https://www.powerelectronicsnews.com/new-allegro-a81415-pmic-simplifies-brake-by-wire-systems/
  5. EDN: Hybrid capacitors target automotive power - https://www.edn.com/hybrid-capacitors-target-automotive-power/
  6. Adafruit / Limor Fried: A practical implementation for a PCIe Gen2/Gen3 1 2 Analog MUX - https://blog.adafruit.com/2026/07/06/a-practical-implementation-for-a-pcie-gen2-gen3-12-analog-mux/
  7. EE Times: The Energy Barrier Reshaping AI Hardware - https://www.eetimes.com/ai-energy-barrier-forces-system-technology-co-optimization/
  8. EE Times: Voyager Spacecraft: The Ultimate Power Management Challenge? - https://www.eetimes.com/voyager-spacecraft-the-ultimate-power-management-challenge/