EMI control and thermal headroom under rising power density and new voltage rails

Engineers who have chased conducted emissions past 30 MHz on a 48 V rail already know that layout parasitics and capacitor self-resonance often dominate before the switch node does. This week three separate publications converge on the same practical constraint: higher bus voltages and tighter rack envelopes are forcing earlier attention to filter topology, package cooling paths, and board-level iteration speed.

The 48 V automotive USB-EPR case shows how conducted-emission test setups must now account for the full power-delivery path rather than just the downstream load. The GaN data-center example illustrates that dual-side cooling only buys margin if the PCB copper and via stack can actually extract the heat; otherwise, the footprint reduction is lost to derating. Feed-through capacitors appear as a direct response to the same parasitic-inductance problem that appears once currents exceed a few amperes at 48 V.

Taken together, the material points to a design sequence that starts with filter placement and thermal vias rather than ending with them after first prototypes fail.

The essentials

48 V automotive USB-EPR conducted-emission behaviour The tutorial walks through a reference design delivering at least 100 W and shows the test setup used to measure conducted emissions on the 48 V rail. Automotive harness inductance and the higher voltage both shift the frequency content of ripple, requiring filter components whose parasitic inductance remains low enough to stay below the limit line.

Dual-side-cooled 650 V GaN for data-center racks Megawatt-scale AI racks are running out of board area and thermal budget before they reach their power limit. The device dissipates heat from both top and bottom surfaces, but the article emphasizes that the PCB layout must still provide adequate copper area and via density to move that heat into the cold plate or heatsink.

Feed-through capacitors as high-frequency EMI barriers When ordinary bypass capacitors lose effectiveness because of series inductance, three-terminal feed-through devices maintain low impedance into the gigahertz range. The article explains their construction and placement rules for enclosures where seams and cable entries otherwise allow radiated energy to escape.

Local PCB prototyping reduces iteration friction Geographic separation between design and fabrication teams adds days or weeks when a layout change is needed to fix an emission or thermal issue. Proximity shortens the loop between measurement, layout edit, and re-test, which matters once power-density targets force multiple board spins.

PCBA test methodology selection Zero-defect manufacturing goals require matching the test strategy to the failure modes that actually appear at higher currents and voltages. The article outlines how in-circuit, functional, and boundary-scan coverage must be weighted when EMI filters and dense power stages occupy the same board area.

Design debates and tensions

Higher bus voltages reduce I²R losses in harnesses but increase the voltage stress across filter components and raise the energy stored in parasitic capacitances. One side argues that 48 V simply demands better common-mode chokes and feed-through parts; the other notes that the same voltage also changes the required creepage and clearance distances, which can offset the wire-gauge savings on the board itself. Data so far favor the filter-first approach only when the layout already includes defined return paths and stitching vias; otherwise, the clearance rules dominate.

Component and industry news

No new component releases with quantified specifications appear in the supplied material. The JESD264 silicon-photonics qualification standard was released by Jedec, but its detailed test conditions and pass/fail criteria are not yet public.

Research and technical advances

No peer-reviewed results with numerical benchmarks on EMI or power devices are present in the supplied sources.

Standards, compliance, and industry policy

The EU Cyber Resilience Act continues to push secure-by-design requirements into embedded firmware and hardware root-of-trust decisions. The practical impact for power and mixed-signal boards is that any microcontroller handling configuration or telemetry must now carry documented vulnerability management processes from the first tape-out.

Quick Radar

  • Delhi grid loss reduction: Utility-scale metering and theft detection cut technical and non-technical losses; the engineering detail lies in the sensor placement and communication reliability rather than the power-electronics content.
  • Local prototyping speed: Proximity to fabrication shortens the feedback loop when emission or thermal fixes require board changes.
  • PCBA test coverage trade-offs: Selecting the right combination of in-circuit and functional test remains a board-specific optimization once dense power stages are present.
  • Silicon photonics qualification: JESD264 provides the first industry-wide reliability framework, but device-level test conditions are still being adopted by suppliers.

Closing

Have you measured conducted emissions on a 48 V rail with the full harness inductance in place, and did the filter topology that worked at 12 V still pass? Compare the via and copper-area assumptions in your last 48 V layout against the thermal paths described for the dual-side-cooled GaN part; the difference usually appears first in the measured case temperature under full load.

Sources

  1. EDN: Power Tips #157: Reducing conducted EMI in 48V automotive USB Type-C EPR designs - https://www.edn.com/power-tips-157-reducing-conducted-emi-in-48v-automotive-usb-type-c-epr-designs/
  2. EDN: Demystifying feed-through capacitors: How to stop EMI in its tracks - https://www.edn.com/demystifying-feed-through-capacitors-how-to-stop-emi-in-its-tracks/
  3. EDN: How a 650-V GaN device shrinks footprint in space-constrained data center racks - https://www.edn.com/how-a-650-v-gan-device-shrinks-footprint-in-space-constrained-data-center-racks/
  4. Embedded.com: Local PCB Prototyping Cuts Delays and Speeds Iterations - https://www.embedded.com/local-pcb-prototyping-cuts-delays-and-speeds-iterations/
  5. EE Times: PCBA Test Strategies: How to Select the Right Methodology and Tester - https://www.eetimes.com/pcba-test-strategies-how-to-select-the-right-methodology-and-tester/
  6. Electronics Weekly: Jedec JESD264 sets out foundation for broader silicon photonics adoption - https://www.electronicsweekly.com/news/jedec-jesd264-sets-out-foundation-for-broader-silicon-photonics-adoption-2026-10/